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Senior Analog Layout Design Engineer

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Interim/Contract
All
All
United Kingdom & ROI
Cambridge UK
£60 per hour. 3 month rolling contract
23.03.2018 12:03 PM
EY18190

An industry-leading ICT company is seeking a Senior Analog Layout Design Engineer to join their UK research team. You will become a member of a world-class analog design team in providing high-performance analog and mixed mode circuits for leading data communication and networking products.

When most companies are downsizing and cutting research budget nowadays, this company's R&D Centres worldwide are buzzing with activities and they’ve become the top patent filers globally. They spare no expense to further scientific progress to gain industry competitiveness. You will join a galaxy of accomplished scientists and be equipped with all the necessary means to focus on the next big innovation, worry-free. Some of their employees describe it as a researcher’s utopia.
 
Your ideas and hard work can benefit 1/3 of the world's population served by this company's technology. So if you eat, sleep and breathe new technologies and are passionate about innovations, please get in touch ASAP!!



The Role

Responsibilities of the Senior Analog Layout Design Engineer:

  • Layout design of a complex high-speed, low-noise mixed-signal IP in 16nm CMOS process
  • Hands-on block-level layout design and verification work, top-level IP floor-planning and integration, IC sign-off and tape-out
  • Work closely with the analogue design team on IP floor-planning, trial layout design and parasitic extraction of critical structures; propose circuit design changes
  • Co-ordinate layout design activities across multiple sites. Delegate block-level layout work when feasible
  • Collaborate with the CAD, process technology, package design and digital back-end teams
  • Document own work and participate in design reviews
  • Provide guidance to junior team members

Profile:
Qualifications for the Senior Analog Layout Design Engineer:

  • Previous experience in the design of high-speed or RF layout in advanced CMOS processes
  • 16nm FinFET experience will be an advantage
  • High-speed ADC layout design experience an advantage
  • Good understanding of high-speed and low-noise layout design techniques and requirements
  • Experience in top-level integration and tape-outs
  • Knowledge of semiconductor device physics and process technology
  • Ability to communicate effectively with circuit and layout designers
  • Ability to work effectively and efficiently in a team environment
  • Fast learner and able to work as part of a team
  • Senior Analog Layout Design Engineer

Candidates must be an EU national eligible to work in this location, ideally already based in the UK.

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